Method of forming a low cost digital variable capacitor

ABSTRACT

A digital variable capacitor package is provided as having a ground plane disposed on predetermined portion of the top surface of a substrate. An elongated signal electrode may also be disposed on the substrate and including a first end defining an input and a second end extending to a substantially central region of the top surface of the substrate. This elongated signal electrode is disposed to be electrically isolated from the ground plane. A number of elongated cantilevers are disposed on the substrate and each include first ends coupled to the second end of the signal electrode and each further include second ends suspended over different predetermined portions of the ground plane. In operation, one or more of the cantilevers may be actuated to move portion thereof into close proximity to the ground plane for providing one or more discrete capacitance values.

STATEMENT OF GOVERNMENT INTEREST

The invention described herein may be manufactured and used by or forthe Government for governmental purposes without the payment of anyroyalty thereon.

FIELD OF THE INVENTION

The present invention relates generally to micro-electromechanical (MEM)systems and microwave components and, more particularly, to a low costdigital variable capacitor.

BACKGROUND OF THE INVENTION

MEM variable capacitors can be implemented in both analog and digitalconfigurations. Analog variable capacitors have the advantage that theycan be tuned to any value in their capacitance range. However, they aresubject to capacitance variations resulting from voltage fluctuations onthe control line. Further, the tuning range of analog variablecapacitors is typically limited by the pull-in phenomena associated withelectrostatic parallel-plate actuators. Digital MEM variable capacitorshave been demonstrated using switching networks with very highcapacitance ratios (>10). Unfortunately, the switches introduce a smallresistance that limits the ultimate Quality (Q) values or Q factors ofthe devices. Further, the size of a switching network and multiplecapacitors limits the maximum frequency for which the device canoperate. Digital MEM variable capacitors have also been implementedusing mechanical standoffs to create capacitors with fixed up and downstates. In these devices, multiple mechanical structures are used tocreate multiple digital states. These devices are controlled usingindividual control lines with one control line designated to each state.This requires a large number of control lines for each digital capacitorand limits the application of the devices in large numbers.

It would, therefore, be desirable to overcome the aforesaid and otherdisadvantages.

SUMMARY OF THE INVENTION

In one aspect of the present invention, set forth is a digital variablecapacitor including a ground plane disposed on a substrate. An elongatedsignal electrode is also disposed on the substrate and includes a firstend defining an input and a second end extending to a substantiallycentral region of the substrate. In this arrangement, the elongatedsignal electrode is disposed to be electrically isolated from the groundplane. A number of elongated cantilevers are disposed on the substrate.Each of the cantilevers have a first end coupled to the second end ofthe signal electrode. Furthermore, each of the cantilevers have a secondend suspended over different predetermined portions of the ground plane.In this arrangement, the first end of the electrode is adapted toreceive one or more control values operative to actuate at least one ofthe number of cantilevers to position the second end thereof inrelatively close proximity to the ground plane for providing at least afirst predetermined capacitance value between the input defined at thefirst end of the signal electrode and the ground plane.

In another aspect of the present invention, set forth is method offorming a digital variable capacitor. The method includes disposing andpatterning a relatively thin metal layer on a relatively thick wafersubstrate to form at least one signal electrode and at least one groundplane region, which includes a notched portion. A sacrificial layer isdisposed and patterned over portions of the signal electrode and theground plane region. At least one dimple may be etched in thesacrificial layer over and substantially aligned with the notched regiondefined on the ground plane region. A relatively thick metal layer maybe disposed over the signal electrode and/or sacrificial layer. Thesacrificial layer may thereafter be etched away for forming a number ofcantilevers. Each of the cantilevers include a first end coupled to asignal electrode and each of the number of cantilevers include a secondend suspended over different predetermined portions of the ground plane.In this arrangement, the signal electrode is adapted to receive one ormore control values operative to actuate at least one of the number ofcantilevers to position the second end thereof in relative closeproximity to the ground plane for providing at least a firstpredetermined capacitance between the signal electrode and the groundplane.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more fully understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 shows an embodiment of the digital variable capacitor inaccordance with the present invention;

FIGS. 2 a and 2 b respectively show a top view of one of the cantileversand a corresponding cross-sectional view of the cantilever and groundplane, which are included on the digital variable capacitor package ofFIG. 1;

FIGS. 3 a-3 f show one embodiment of a method of forming the digitalvariable capacitor of FIG. 1;

FIG. 4 shows an exemplary sequence of operation of the cantileversincluded on the digital variable capacitor package of FIG. 1;

FIGS. 5 a and 5 b respectively show a spring force model used todetermine dimensions of the cantilevers included on the digital variablecapacitor package of FIG. 1;

FIGS. 6 a and 6 b respectively show an S-parameter magnitude and phasefor all four states of the cantilevers included on the digital variablecapacitor package of FIG. 1;

FIG. 7 shows a graph representing four possible digital capacitancestates of the digital variable capacitor package of FIG. 1;

FIG. 8 shows a table (Table-1) representing exemplary digitalcapacitance values corresponding to each of the four possible digitalcapacitance states of FIG. 7; and

FIG. 9 shows a table (Table-2) representing exemplary physical dimensionvalues and bias voltages for each of the cantilevers included on thedigital variable capacitor package of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a digital variable capacitor and methodof manufacturing the same. The digital variable capacitor is constructedand arranged to provide a number of discrete capacitance values using asingle control electrode, which reduces dimensions and complexity. Thedigital variable capacitor may be employed for phase shifting, impedancematching and/or other tuning related features for a number of relativelyhigh frequency transmission lines, devices and systems. As will bedescribed in further detail below, suffice it say here, the digitalvariable capacitor includes three separate cantilevers that areconstructed and arranged to pull-in at three different voltages, such as25 Volts, 31 Volts, and 35 Volts, which operates to provide fourdistinct capacitance states (2-bit equivalent).

Referring now to FIG. 1, shown is one embodiment of the digital variablecapacitor package 10 in accordance with principles of the presentinvention. In the illustrative embodiment, the digital variablecapacitor package 10 includes a substrate 12. In an embodiment, thesubstrate 12 can be formed of sapphire, glass or other sturdy dielectricmaterials and may include the dimensions of approximately 535 μm by 586μm. A ground plane 14 may be disposed along an edge region 16 of thesubstrate 12 and may include first, second and third stepped regions 14a, 14 b, 14 c.

A single elongated electrode 18 is also disposed on the substrate 12 andincludes a first end 18 a defining an input and a second end 18 bextending to a central region of the substrate 12. The second end 18 bof the electrode 18 is electrically coupled to first ends 20 a, 22 a, 24a of respective first, second and third elongated cantilevers 20, 22,24. A second end 20 b, 22 b, 24 b of each of the respective first,second and third elongated cantilevers 20, 22, 24 includes a capacitanceplate portion 20 b′, 22 b′, 24 b′. In the illustrative embodiment, afirst digital capacitor 26 is formed between the capacitance plateportion 20 b defined at the second end 20 b of the first cantilever 20and the first stepped portion 14 a of the ground plane 14. Further, asecond digital capacitor 28 is formed between the capacitance plateportion 22 b′ defined at the second end 22 b of the second cantilever 22and the second stepped portion 14 b of the ground plane 14. Similarly, athird digital capacitor 30 is formed between the capacitance plateportion 24 b′ defined at the second end 24 b of the third cantilever 24and the third stepped 14 c portion of the ground plane 14.

Referring to FIGS. 2 a and 2 b collectively, respectively shown are atop plan view of the first cantilever 20 and a cross-sectional view ofthe first cantilever 20 taken through lines a-a (FIG. 1). It should beunderstood that the first cantilever 20 is shown and described in FIGS.2 a and 2 b for illustrative purposes and that the second 22 and third24 cantilevers may be similarly constructed and arranged. In FIG. 2 a,the first cantilever 20 includes a support portion 32 and a capacitanceplate portion 20 b′. The support portion 32 of the first cantilever 20includes a pair of parallel support members 32 a, 32 b, each of whichincludes a length I_(b) and a width W_(b). The pair of support member 32a, 32 b are adapted to receive a voltage potential from a D.C. controlsource (not shown), via the elongated electrode 18 (FIG. 1), and todeflect, deform and/or otherwise bend downwardly a predetermineddistance based on a function of their dimensions, i.e., length I_(b) anda width W_(b), to position the capacitance plate portion 20 b′ in closeproximity to the corresponding stepped portion 14 a of the ground plane14.

The capacitance plate portion 20 b′ of the first cantilever 20 similarlyincludes a predetermined length I_(c) and width W_(c). The length I_(c)and width W_(c) of the capacitance plate portion 20 b of the firstcantilever 20 may be adjusted to form a predetermined capacitancebetween the capacitance plate portion 20 b and corresponding steppedportion 14 a of the ground plane 14 when the pair of support member 32a, 32 b are actuated to position the capacitance plate portion 20 b′ inclose proximity to the stepped portion 14 a of the ground plane 14, asdescribed above.

In an embodiment, each pair of parallel support members associated witheach of the first, second and third cantilevers 20, 22, 24 includedifferent dimensions to provide for adjustment as to the pull-in voltageof each corresponding capacitance plate portion 20 b′, 22 b′, 24 b′. Forexample, dimensions of the support members (eg., support members 32 a,32 b) and the associated pull-in voltages are provided in Table 1. Eachcapacitance plate portion 20 b′, 22 b′, 24 b′ associated with the first,second and third cantilevers 20, 22, 24 include equivalent dimensions ofapproximately l_(c)=100 μm and W_(c)=75 μm.

At least one dimple 34 may be formed on a bottom surface 20 b″ of thecapacitance plate portion 20 b′, which faces the stepped region 14 a ofthe ground plane 14. The dimple 34 formed on the bottom portion 20 b″ ofthe capacitance plate portion 20 b′ is dimensioned to be accepted into anotched region 36 formed on the stepped region 14 a of the ground plane14 for providing a positive downward stop position for the capacitiveplate portion 20 b′ of the first cantilever 20.

FIGS. 3 a through 3 e show one embodiment of a method 100 for formingthe digital variable capacitor 10 of the present invention. Generally,the digital variable capacitor package 10 is fabricated using asacrificial release process designed to fabricate metal contactswitches. The method 100 may use four layers and five photolithographymasks. In order to simplify the description of the method 100, FIGS. 3 athrough 3 e illustrate a cross-section view of the fabrication processfor the first cantilever 20 and although the second and third cantilever22, 24 are not specifically shown, it should be understood that thesecond and third cantilevers are present and are similarly constructedand arranged as the first cantilever 20.

In FIGS. 3 a and 3 b, fabrication begins at step 110 with the depositionof a thin gold layer (≈0.3 μm) on the substrate 12 to form the controlsignal electrode and ground plane. In FIG. 3 c and at step 120, anoptional resistor layer may be disposed for forming resistive biaslines. Although the optional resistor layer is not shown, it should beunderstood that the optional resistor layer may be disposed when banksof capacitors are going to be used simultaneously. Resistive bias linesmay be used as RF blocks, and can be used equally well for one or moredevices. The resistor layer may not be needed for some applications ofdigital variable capacitor package, however, if the capacitor isimplemented into microwave circuits, resistive bias lines may becomenecessary. The resistor layer is followed by a sacrificial layer 54 ofpolymethylglutarimide (PMGI). In an embodiment, the sacrificial layer 54may be approximately 3.0 μm in thickness.

In FIG. 3 d and at step 130, a dimple 56 is then etched into thesacrificial layer 54 to a depth of approximately 1.0 μm. In FIG. 3 e andat step 140, a relatively thick layer of gold 58 or other suitable metalor metal alloy may be disposed over the control signal electrode 18 andsacrificial layer 54 using an electroplating process. In an embodiment,the relatively thick layer of gold 58 or other suitable metal or metalalloy may be approximately 5.0 μm in thickness. Thereafter, therelatively thick layer of gold 58 or other suitable metal or metal alloymay be may be patterned to form the first cantilever 20 and/or any othermechanical devices, as shown below with respect to FIG. 3 f.

In FIG. 3 f and at step 150, a wet chemical etching and/or solventprocess is employed to remove the sacrificial layer 54, which operatesto free the first cantilever 20 and/or any other mechanical structuresformed on the substrate 12. Optionally, the wet chemical etching and/orsolvent process may be followed by a drying process, which uses a CO₂critical point dryer to minimize stiction while drying the digitalvariable capacitance package 10. In an embodiment, a PMGI strippingagent may be used during the wet chemical etching and/or solvent processfor removal of the sacrificial layer 54.

Referring to FIG. 4, shown is a cross sectional view of each of thefirst, second and third cantilevers 20, 22, 24, respectively takenthrough lines a-a, b-b and c-c of FIG. 1. The first, second and thirdcantilevers 20, 22, 24, are constructed and arranged to sequentiallypull in or actuate to an on-state when an increasing D.C. controlvoltage is applied to the signal electrode 18 (FIG. 1). In FIG. 4, thecolumns represents each of the first, second and third cantilevers andthe rows represent the first, second and third cantilevers 20, 22, 24 invarious states (e.g., digital high state or digital low state).

In the exemplary embodiment, the sequence of operation of the digitalvariable capacitor package 10 includes State-0, as shown in row 60,representing the first, second and third cantilevers 20, 22, 24 in offstates (i.e., digital states: 0,0,0). State-1, as shown in row 70,represents the first cantilever 20 actuated to an on-state, while thesecond and third cantilevers 22, 24 are in a non-actuated or off-state(i.e., digital states: 1,0,0). State-2 as shown in row 80, representsthe first and second cantilevers 20, 22 actuated to an on-state, whilethe third cantilever 24 is in a non-actuated or off-state (i.e., digitalstates: 1,1,0). State-3, as shown in row 90, represents the first,second and third cantilevers 20, 22, 24 actuated to an on-state (i.e.,digital states: 1,1,1).

The first, second and third cantilevers 20, 22, 24 are constructed andarranged to pull-in at voltage levels below 40 Volts, and the pull-involtages are all separated by at least 2.5 Volts. The pull-in voltage ofthe first, second and third cantilevers 20, 22, 24 may be calculatedusing a one dimensional linear spring model, as shown in FIGS. 5 a and 5b. This model makes three simplifying assumptions: first, that the forceapplied to each cantilever 20, 22, or 24 is a point force applied to thecantilever 20, 22, or 24 at a distance, α·l_(b), from the cantileversupport member; such as support members 32 a and 32 b of FIG. 2 a,second that the spring constant of the support region can be assumedvalid for this entire length, and third that the force can be calculatedassuming that the gap “g” (FIG. 2 b) is constant across the capacitorplate region. These assumptions introduce systematic errors into thecalculation of the pull-in voltage. However, beam thickness and the gapacross a fabricated wafer result in variations in the pull-in voltage onthe order of ±10%. In addition, run to run variation of the pull-involtage may be greater than ±15%. This modeling is directed to verifyingand ensuring that the three capacitors (e.g., first, second, and thirddigital capacitors 26, 28, 30 (FIG. 1) of each of the first, second andthird cantilevers 20, 22, 24) have separate pull-in voltages to ensurefour distinct capacitance states as shown and described above withrespect to FIG. 4.

The spring constant, k_(sp), is calculated as $\begin{matrix}{k_{sp} = \frac{3 \cdot E \cdot I}{\left( {\alpha \cdot 1_{b}} \right)^{3}}} & (1)\end{matrix}$where E is the Young's modulus of gold (70 GPa), I is the moment ofinertia as calculated below, and α·l_(b) is effective length of thebeam, also calculated below. As described above, it is assumed that themoment of inertia of the spring is constant over the entire effectivelength. The moment of inertia is then calculated as follows:$\begin{matrix}{I = \frac{2 \cdot w_{b} \cdot t^{3}}{12}} & (2)\end{matrix}$where 2·w_(b) is the width of the support cross section and t is thethickness of the beam metal. This value is accurate for the supportregion of the cantilever, but is not accurate for the capacitor model.In the first, second and third cantilevers 20, 22, 24 of the presentinvention, the moment of inertia in the support member region (32 ofFIG. 2 a) may be approximately 1.43, 1.43, and 1.11 times the moment ofinertia in the capacitor region (20 b of FIG. 2 a) for the first, secondand third cantilevers 20, 22, 24, respectively. However, the bendingmoment applied to each cantilever 20, 22, or 24 has its maximum value inthe support region 32 and thus the resulting error is a very smallunderestimate of the spring constant. The effective length of eachcantilever is α·lb. The factor α is calculated as: $\begin{matrix}{\alpha = {1 + \frac{1_{c}}{2 \cdot 1_{b}}}} & (3)\end{matrix}$where l_(b) and l_(c) are the lengths of the support members 32 a, 32 b(FIG. 2 a) and capacitor plate regions 20 b (FIG. 2 a), respectively.This value is set so that the moment in the support region 32 isaccurately calculated for an equally distributed force in the capacitorplate region 20 b′. The moment in the capacitor plate region 20 b′ isnot accurate, but as mentioned, the moment in this region is relativelylow and does not have a large influence on the total deflection of thefirst, second or third cantilevers 20, 22, 24. Utilizing the equationsabove, the spring constant is calculated for each of the first, secondand third cantilevers 20, 22, 24. Finally, the pull-in voltage iscalculated as: $\begin{matrix}{V_{pi} = \sqrt{\frac{4 \cdot k_{sp} \cdot g_{0}^{3}}{27 \cdot ɛ_{0} \cdot 1_{c} \cdot w_{c}}}} & (4)\end{matrix}$where σ₀ is the permittivity of free space and g₀ is the capacitor gap(3.0 μm) at zero volts. The calculated and measured pull-in voltages areprovided in Table 1 (See FIG. 8).

FIGS. 6 a and 6 b respectively show the S-parameter magnitude and phasefor all four states: 0V—all up, 19 V—1 down, 28 V—2 down, 32 V—all down,40 V—all down. The magnitudes of all the states are almost identicalexcept for the all up state which has the lowest loss, and the 2 down(28V) state which shows an increased loss around 40 GHz. Furthermore,shown is the measured magnitude and phase for all four states and fivevoltages. As can be seen, the four states are clearly defined while thetwo measurements (32V and 40V) in the all capacitor down state arevirtually identical. In addition to S-parameters, phase versus timemeasurements were taken at a fixed frequency of 20 GHz. Thesemeasurements were taken with the same set up, however instead of a DCbias, a low frequency (f<2 Hz) triangle wave with a 0-40 V amplitude maybe applied to the capacitor regions 26, 28, 30 (FIG. 1). Over a 5 secondinterval, the phase of S11 maybe recorded. This measurement, allows thegeneration of a phase versus voltage plot by matching the known biasvoltage up with the measured phase value. Further, this measurementprovides a good method for showing all four capacitive states.

FIG. 7 shows the phase versus voltage plot that is derived from thismeasurement. All four states are clearly defined, and the pull-involtages are spaced reasonably well.

The digital variable capacitor 10 of the present invention may be ofinterest to microwave circuit designers because it provides a higherquality factor (Q>100) than other integrated reactive tuning devices(Q<50) at frequencies above XX GHz. In addition, the digital variablecapacitor 10 has been shown to have high capacitance ratios (>1.5) andrelatively high self-resonant frequencies (>40 GHz). Further, thedigital variable capacitor package 10 includes exceptional linearitywith respect to microwave signal power. The overall high performance ofthis device is very promising for applications including voltagecontrolled oscillators, tunable filters, and tunable matching networks.

The digital variable capacitor 10 of the present invention may be widelyused in microwave and wireless systems as reactive tuning elements.Furthermore, the digital variable capacitor 10 may be employed as atuning element for a voltage controlled oscillator. Varying thecapacitance in the circuit varies the center frequency of theoscillator. Another common example may include using the digitalvariable capacitor 10 in phase shifters for phased array antennas. Yetanother example is the use of the digital variable capacitor 10 intuning circuits for matching an input feed to an antenna over a widebandwidth.

The digital variable capacitor 10 of the present invention may also beused for applications at frequencies in the microwave to millimeter-wavefrequency ranges. Of particular value is the discrete capacitance statewhich is provided by sequentially actuating each of the first, secondand third cantilevers 20, 22, 24. In applications such as radar, theperformance of the system is very sensitive to phase variations inelements such as the phase shifter.

As compared to traditional variable capacitors, the digital variablecapacitor 10 of the present invention offers a good tuning ratio,relatively high Q, and discrete capacitance states. The tuning ratio of1.7:1 can be improved significantly by increasing the initial air gap,or decreasing the final landing height. These changes are readilyimplemented and allow designers a greater degree of freedom thantraditional designs. The high Q of this device is inherent to the metalair metal capacitor design. The thick metal layer and compact sizeprovide very low losses. This directly translates into improvedperformance when integrated into systems. Finally, the discretecapacitance states, have significant potential impact in areas wherephase noise is a critical parameter, specifically radar.

One skilled in the art will appreciate further features and advantagesof the invention based on the above-described embodiments. Accordingly,the invention is not to be limited by what has been particularly shownand described, except as indicated by the appended claims. Allpublications and references cited herein are expressly incorporatedherein by reference in their entirety.

1. A method of forming a digital variable capacitor, comprising: (a)disposing and patterning a relatively thin metal layer on a relativelythick wafer substrate to form at least one signal electrode and at leastone ground plane region including a notched portion; (b) disposing andpatterning a sacrificial layer over portions of the signal electrode andthe ground plane region; (c) etching at least one dimple in thesacrificial layer over and substantially aligned with the notched regiondefined on the ground plane region; (d) disposing a relatively thickmetal layer over the signal electrode sacrificial layer; and (e) etchingaway the sacrificial layer for forming a number of cantilevers eachhaving first ends coupled to the signal electrode and each of the numberof cantilevers having second ends suspended over different predeterminedportions of the ground plane, wherein the signal electrode is adapted toreceive one or more control values operative to actuate at least one ofthe number of cantilevers to position the second end thereof in relativeclose proximity to the ground plane for providing at least a firstpredetermined capacitance between the signal electrode and the groundplane.
 2. The method of forming a digital variable capacitor of claim 1,wherein step (a) further includes disposing and patterning a relativelythin gold metal layer on the relatively thick wafer substrate to formthe at least one signal electrode and the at least one ground planeregion including the notched portion.
 3. The method of forming a digitalvariable capacitor of claim 2, wherein step (a) further includes usingan evaporation process for disposing the thin gold metal layer.
 4. Themethod of forming a digital variable capacitor of claim 3, wherein step(a) further includes using a lift off process for patterning the thingold metal layer.
 5. The method of forming a digital variable capacitorpackage of claim 1, wherein step (b) further includes disposing andpatterning the sacrificial layer including a layer ofpolymethylglutarimide (PMGI) over portions of the signal electrode andthe ground plane region.
 6. The method of forming a digital variablecapacitor of claim 5, wherein step (b) further includes disposing thelayer of PMGI over portions of the signal electrode and the ground planeregion using a spin coating process and permitting the PMGI to cure. 7.The method of forming a digital variable capacitor in of claim 6,wherein step (b) further includes patterning the layer of PMGI using aphoto-lithographic process.
 8. The method of forming a digital variablecapacitor of claim 1, wherein step (c) further includes etching thedimple using a photolithographic process to a depth of approximately onemicrometer.
 9. The method of forming a digital variable capacitor ofclaim 1, wherein step (d) further includes disposing the relativelythick gold layer using an electroplating process.
 10. The method offorming a digital variable capacitor of claim 1, wherein step (e)further includes etching away the sacrificial layer using PMGI stripperfor forming the number of cantilevers.